Published May 1992 | Version v1
Report Restricted

A pipelined multiranging integrator and encoder ASIC for fast digitization of photomultiplier tube signals

Description

A new full custom chip is being designed using the Orbit 2 micron ''BiCMOS'' process to provide a wide range fast digital readout of Photomultiplier Tubes. The goal is to obtain a digitized PMT signal with a 18--20 bit dynamic range and 8 bits of accuracy in a floating point number format every 16 ns. The chip is DC coupled to a PMT and uses a four-way gated integrator and encoder to form a 4 bit binary number which is the exponent of the floating point number. Simultaneous processing of the PMT signal on binary weighted scales provides a pipelined analog signal to a single FADC which generates the floating point number mantissa. The current state of development of this new chip and results from several test chips are presented in this paper. 3 refs

Availability note (English)

MF available from INIS under the Report Number; OSTI as DE92016348; NTIS; INIS; US Govt. Printing Office Dep.

Files

Restricted

The record is publicly accessible, but files are restricted to users with access.

Additional details

Publishing Information

Imprint Pagination
14 p.
Report number
FNAL/C--92/148

Conference

Title
2. annual conference on electronics for future colliders.
Dates
19-21 May 1992.
Place
Chestnut Ridge, NY (United States).

Optional Information

Contract/Grant/Project number
Contract AC02-76CH03000
Funding organization
USDOE, Washington, DC (United States).
Secondary number(s)
CONF-9205210--1.