Published December 1, 2013
| Version v1
Journal article
ESD performance of LDMOS with source-bulk layout structure optimization
Creators
- 1. State Key Laboratory of Electronic Thin Film and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China)
Description
To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vt1 is reduced from 55.53 to 50.69 V. (semiconductor devices)
Availability note (English)
Available from http://dx.doi.org/10.1088/1674-4926/34/12/124003Additional details
Identifiers
Publishing Information
- Journal Title
- Journal of Semiconductors
- Journal Volume
- 34
- Journal Issue
- 12
- Journal Page Range
- [5 p.]
- ISSN
- 1674-4926
INIS
- Country of Publication
- United Kingdom
- Country of Input or Organization
- International Atomic Energy Agency (IAEA)
- INIS RN
- 47018466
- Subject category
- S36: MATERIALS SCIENCE;
- Descriptors DEI
- COMPARATIVE EVALUATIONS; COMPUTERIZED SIMULATION; EQUIPMENT; SAFETY; SEMICONDUCTOR DEVICES
- Descriptors DEC
- EVALUATION; SIMULATION