Published 2019 | Version v1
Book

Evaluation of electrical characteristics with circuit co-design for ultra low power subthreshold logic

  • 1. Amity University, Gwalior (India)
  • 2. Sagar Institute of Research and Technology, Bhopal (India)

Description

Scaling of the transistor is a prime thrust for development of semiconductor industries. In this paper we have evaluate the impact of ION and IOFF current from 7nm to 20nm of FinFET technology, in this paper we have seen the impact of back gate biasing, while keeping the front Gate constant and see the variation in ION and IOFF current. All the results were calculated in signal N-FinFET and P-FinFET transistor in HP and LSTP model by using HSPICE simulator. From the simulation results it is observe that when back Gate bias is applied and calculate the ION and IOFF current, but there is no variation in the ION and IOFF current both in HP and LSTP model of FinFET, variation is shown in as we move from 7nm to 20 nm technology. (author)

Part of:
Proceedings of the first international conference on advances in nanomaterials and devices for energy and environment: abstract proceeding

Additional details

Publishing Information

Publisher
Indian Institute of Information Technology and Management
Imprint Place
Gwalior (India)
Imprint Title
Proceedings of the first international conference on advances in nanomaterials and devices for energy and environment: abstract proceeding
Imprint Pagination
[179 p.]
Journal Page Range
[1 p.]

Conference

Title
international conference on advances in nanomaterials and devices for energy and environment
Acronym
ICAN-2019
Dates
27-29 Jan 2019
Place
Gwalior (India)

Optional Information

Notes
Article ID P-160