Published May 1989
| Version v1
Journal article
Electrical resistance as a limiting factor for high performance computer packaging
Description
A formula has been derived for the estimation of the packaging performance limit caused by wire resistance. This is applicable to the evaluation of the usefulness of high-temperature superconductors for improving computer packaging performance. The theoretical limit of wire delay caused by resistance is estimated to be several picoseconds from the case studies carried out by using the formulation
Additional details
Publishing Information
- Journal Title
- IEEE Circuits and Devices
- Journal Volume
- 5
- Journal Issue
- 3
- Series
- IEEE Circuits Devices.
- Journal Page Range
- 22-26
- ISSN
- 8755-3996
- CODEN
- ICDME
INIS
- Country of Publication
- United States
- Country of Input or Organization
- United States
- INIS RN
- 20070755
- Subject category
- S71: CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; S75: CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY;
- Resource subtype / Literary indicator
- Numerical Data
- Descriptors DEI
- ALGORITHMS; COMPUTERS; ELECTRIC CONDUCTIVITY; HIGH TEMPERATURE; PERFORMANCE; SPECIFICATIONS; SUPERCONDUCTING WIRES; SUPERCONDUCTIVITY; THEORETICAL DATA
- Descriptors DEC
- DATA; ELECTRICAL PROPERTIES; INFORMATION; NUMERICAL DATA; PHYSICAL PROPERTIES; WIRES