Trends in VLSI processing

The scaling laws for MOS transistors are briefly reviewed and physical limitations like velocity saturation and mobility degradation are explained. The maximum operating voltage is limited by substrate currents, hot carrier effects, punchthrough and snapback phenomena. The problem related to the increasing interconnect delay time is mentioned. Trends in CMOS and BICMOS are pointed out and the choice between p-well, n-well or twin well is discussed. A few remarks are made about the SOI technology (Silicon On Insulator). Finally some new developments in micropatterning and in VLSI materials such as silicides and refractory metals are addressed and their implementation in full processes is discussed. (orig.)