Gamma irradiation damage on the vertical JFET transistors fabricated at the IMB-CNM

A new vertical JFET technology, based on a 3D trenched design, has been developed at the IMB-CNM. These transistors are conceived to work as rad-hard protection switches in the renewed High Voltage powering scheme for the Upgrade ATLAS ITk strip detectors. The first fabricated wafers have been fully characterized and the V-JFET performance is very close to the required specifications, showing excellent agreement with simulations. In this work the performance of the fabricated prototypes is tested under harsh ionizing radiation conditions. The variation of the main figures of merit is evaluated as a function of the Total Ionising Dose (TID) and the impact of different design parameters and fabrication strategies are compared. A final study, performed with the aid of TCAD simulations, is also included to understand the effects of the ionization damage observed on the V-JFET performance.