Fabrication technology for a high-density Josephson LSI using an electron cyclotron resonance etching technique and a bias-sputtering planarization

To realize future high-density Josephson LSIs, an increase of the thickness of a junction counter electrode and planarization of an insulation layer are required. Using an improved electron cyclotron resonance plasma source, the counter electrode thickness can be increased to 300 nm with good junction quality and uniformity. With this method, a 0.4 μm wide Nb line was also obtained. A bias-sputtering technique is studied as a planarization method. By the improved bias-sputtering planarization technique, the planarization ratio of 23% is obtained independent of the underlying line width. These results are promising for future high-density Josephson LSI fabrication. (author)