Commercial highly parallel signal processors on-line?

For experiments on future hadron colliders event rates of 108 events/s and data volumes of 1 megabytes/recorded event are expected. The speed-up of several orders of magnitude in processing power over today's on-line systems has to come mainly from progress in architectures. We have identified some representative triggering and data compaction algorithms and have started to look into matching architectures. We are considering commercially available signal processing architectures. In this paper we will mainly concentrate on a system of algorithmically dedicated pipeline processors. Our aim is to understand the existing parallel architectures to be able to embed them into a future readout system, if suitable. (orig.)