Published July 1, 2019 | Version v1
Journal article

Deep levels in metal–oxide–semiconductor capacitors fabricated on n-type In0.53Ga0.47As lattice matched to InP substrates

  • 1. Imec, Kapeldreef 75, B-3001 Leuven (Belgium)
  • 2. On Leave From State Key Lab of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, Sichuan (China)

Description

In this work, deep levels present in n-type In0.53Ga0.47As hetero-epitaxial layers grown lattice-matched on n-type InP substrates by molecular beam epitaxy have been studied by deep-level transient spectroscopy (DLTS). Metal–oxide–semiconductor capacitors are employed, based on an Al2O3 gate oxide. It is shown that a single, near mid-gap electron trap dominates the DLT-spectra, whatever the surface pre-or post-gate oxide deposition treatment. At the same time, it is shown that the deep level parameters vary significantly from capacitor to capacitor and from wafer to wafer. Only after Forming Gas Annealing, a stable value for the activation energy of 0.39 ± 0.01 eV is obtained. These results are tentatively interpreted in terms of antisite defects in the epitaxial layer, which form a family of related complexes with close deep-level parameters. (paper)

Availability note (English)

Available from http://dx.doi.org/10.1088/1361-6641/ab2481

Additional details

Identifiers

Publishing Information

Journal Title
Semiconductor Science and Technology
Journal Volume
34
Journal Issue
7
Journal Page Range
[7 p.]
ISSN
0268-1242
CODEN
SSTEET