Performance simulation of a three-dimensional nanoscale field-effect diode

The modified field effect diode (FED) can provide orders of magnitude larger ratio compared to regular MOSFETs at sub-100 nm channel lengths. However, fabrication of the modified FED requires implantation of very thin and highly doped n- and p-type regions on top of each other, which is a major practical problem to overcome. An improved sub-100 nm channel length 3D configuration of the FED is proposed and simulated using Silvaco TCAD software. Fabrication of this configuration is compatible with a regular CMOS process while providing a larger ION/IOFF ratio. The current–voltage (I–V) characteristics of this structure is obtained and compared with that of a semiconductor-on-insulator MOSFET (SOI-MOSFET) with the same dimensions numerically. Simulation results indicate that the ION/IOFF ratio of the 3D FED is five orders of magnitude larger than that of the comparable SOI-MOSFET