Circuit implementation of mechanism for charge-sharing suppression for photon- counting pixel arrays

This work proposes an efficient circuit implementation of a mechanism for charge-sharing suppression in photon-counting pixel arrays based on current-mode circuits for the analog parts. The additional circuits needed for charge-sharing suppression in a four-pixel cluster, leads to an increase in power consumption of 36% and only a marginal increase in circuit area. The implemented pixel which window-discrimination, managing charge-sharing in a four-pixel cluster and with an event-counter of 13 bits, consists of 300 transistors and has a power consumption of 2.7 μw when idle. It is implemented in a 120 nm CMOS process and the presented results are based on simulations. (Author)