SEU characterization of hardened CMOS SRAMS using statistical analysis of feedback delay in memory cells

The amount of feedback delay introduced by the polysilicon cell resistors in a SEU hardened CMOS SR is not identical for all cells in a memory chip. This is confirmed by write-time measurements. The effect of the variance in the normal distribution of feedback delay has become pronounced because of the large number of resistors in state-of-the art memory chips. Consequently, statistical analysis of the distribution of feedback delay is useful for proper interpretation of SEU test data to quantify device response for confident hardness assurance