Published November 2011 | Version v1
Report

Study of radiation effects on semiconductor devices

  • 1. Japan Aerospace Exploration Agency (JAXA), Aerospace Research and Development Directorate, Chofu, Tokyo (Japan)
  • 2. Ryoei Technica Corp., Kamakura, Kanagawa (Japan)
  • 3. National Inst. of Radiological Sciences, Chiba, Chiba (Japan)

Description

Due to the demand for high integration and scaling down, recent integrated circuits have been designed with the design rule less than 100 nm. SEUs (Single-Event Upset) and SETs (Single-Event Transient) are serious problems for those devices because of the lower supply voltage and the lower threshold voltage of the transistors that makes more sensitive to smaller charge generated by an ion passage. To attain higher radiation tolerance for high integrated circuits, a DICE (Dual Interlocked Storage Cell)-based flip-flop with an SET pulse discriminator circuit on a 90-nm bulk CMOS was designed and fabricated and its performance was examined through radiation testing. SEU/SET sensitivity in the angular irradiation was measured and analyzed in this study. The test of edge-on irradiation was performed for the first time and the importance of the angular irradiation for the memory cells that have redundant memory nodes was demonstrated. (author)

Part of:
2010 annual report of the research project with heavy ions at NIRS-HIMAC

Additional details

Publishing Information

Imprint Title
2009 annual report of the research project with heavy ions at NIRS-HIMAC
Imprint Pagination
322 p.
Journal Page Range
p. 169-170
Report number
NIRS-M--244

Optional Information

Notes
This record replaces 45054826
Secondary number(s)
HIMAC--136