Published May 1, 2018
| Version v1
Journal article
A survey on multipliers, adders and adiabatic logic styles suitable for power reduction
Creators
- 1. Department of Electronics and Communication Engineering, RMK Engineering College, Kavaraipettai, Tamilnadu (India)
Description
Low power circuits and designs are the need of the hour as they find applications in electronic components which have power efficient processing capabilities. High speed processors are power consuming and multipliers contribute to a maximum extent for this power consumption. Thus, to achieve low power designs, adiabatic logic is one of the noted technologies in this regard. Adiabatic logic can be implemented for different types of circuit designs and this paper concentrates on a survey of various multipliers and adders that can be modified into a low power multiplier using adiabatic logic. (paper)
Availability note (English)
Available from http://dx.doi.org/10.1088/1742-6596/1026/1/012008Additional details
Identifiers
Publishing Information
- Journal Title
- Journal of Physics. Conference Series (Online)
- Journal Volume
- 1026
- Journal Issue
- 1
- Journal Page Range
- [5 p.]
- ISSN
- 1742-6596
Conference
- Title
- International Conference on Electronics, Communications and Control Engineering (ICECC)
- Dates
- 6-8 Mar 2018
- Place
- Male (Maldives)
INIS
- Country of Publication
- United Kingdom
- Country of Input or Organization
- International Atomic Energy Agency (IAEA)
- INIS RN
- 52080365
- Subject category
- S32: ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATION;
- Resource subtype / Literary indicator
- Conference
- Descriptors DEI
- ELECTRONIC CIRCUITS; ELECTRONIC EQUIPMENT; ENERGY CONSUMPTION; ENERGY EFFICIENCY; PROCESSING
- Descriptors DEC
- EFFICIENCY; EQUIPMENT