Front end electronics for silicon tungsten calorimeter

This document given at the conference as a power-point presentation has the following structure: 1. Requirements; 2. A design; 3. Adaptive stage; 4. Shaper; 5. Coding; 6. First ideas for ADC. The requirements are follows: - Maximum energy, up to 1 TeV. => bunch crossing 150 ns; - Time signal, between 20 ns-60 ns; - Train = 3000 bunch crossing; - One Train every 200 ms; - Dynamic = signal/noise = 14-15 bits; - Accuracy, 0.4 % i.e. 8 bits; - 30 Millions channels with 4 mW/channel max; - 128 channels/chip i.e. 240.000 chips. Particularly addressed are some ideas relating to accuracy vs. dynamics to get multi gain with choice of gain, namely: No preamplifier with multi-gain; Shaper multi-gain, Vout = energy; Energy value, only one measurement. In conclusion for the technology implied the choice was Cmos and SiGe, but for the moment, AMS 0.8 μm BiCMOS was used. Good results were obtained in testing the amplifier, improvement is required in the linearity of common to differential mode, while for ADC the consumption was either bipolar or Cmos. Also, conclusion concerning the multiplexer and analog memory is given