Published June 1986
| Version v1
Journal article
Front end processing for a 100 MHZ Flash-ADC-System
- 1. Physikalisches Institut, Universitat Heidelberg, Philosophenweg 12, D-6900 Heidelberg
Description
An intelligent interface for readout of a high speed (100 MHz), multichannel Flash-ADC System is described. 3072 FADC channels are controlled and read by a system of 34 microprocessors M68000 placed at two different hierarchical levels. In addition to the readout itself, the processors perform a detailed pulse shape analysis necessary for a compact and manageable data format. The purpose of the system is to exploit the good double tract separation and time resolution provided by Flash-ADCs in conjunction with large drift chamber detectors such as JADE at PETRA and OPAL at LEP. Details of the system presently being installed at JADE are reviewed
Additional details
Publishing Information
- Journal Title
- IEEE Trans. Nucl. Sci.
- Journal Volume
- NS-33
- Journal Issue
- 3
- Series
- IEEE Trans. Nucl. Sci.
- Journal Page Range
- 1066-1070
- ISSN
- 0018-9499
- CODEN
- IETNA
INIS
- Country of Publication
- United States
- Country of Input or Organization
- United States
- INIS RN
- 17083011
- Subject category
- S43: PARTICLE ACCELERATORS; S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY;
- Descriptors DEI
- ANALOG-TO-DIGITAL CONVERTERS; DRIFT CHAMBERS; EQUIPMENT INTERFACES; LEP STORAGE RINGS; MHZ RANGE 100-1000; MICROPROCESSORS; MULTI-CHANNEL ANALYZERS; PETRA STORAGE RING; PULSES; READOUT SYSTEMS; TIME RESOLUTION
- Descriptors DEC
- ELECTRONIC CIRCUITS; ELECTRONIC EQUIPMENT; EQUIPMENT; FREQUENCY RANGE; MEASURING INSTRUMENTS; MHZ RANGE; MICROELECTRONIC CIRCUITS; MULTIWIRE PROPORTIONAL CHAMBER; PROPORTIONAL COUNTERS; PULSE ANALYZERS; RADIATION DETECTORS; RESOLUTION; STORAGE RINGS; TIMING PROPERTIES