A new self-aligning process for whole-wafer tunnel junction fabrication

The authors have developed a new processing route for whole-wafer tunnel junctions which offers significant advantages over existing methods. This route allows the preparation of planar tunnel junctions with just two lithographic steps and largely eliminates the inherent capacitance and potential failure problems associated with overlap between the base-electrode and the counter-electrode metallization common to all existing routes. Results of preliminary trials of this method are presented and possible future developments discussed