The SLAC scanner processor: A FASTBUS for data collection and processing
- 1. Stanford Linear Accelerator Center, Stanford, CA
Description
A new, general purpose, programmable FASTBUS module, the SLAC Scanner Processor (SSP), is introduced. Both hardware and software elements of SSP operation are discussed. The role of the SSP within the upgraded Mark II Detector at SLAC is described. The SLAC Scanner Processor (or SSP) is a general-purpose, high-speed, programmable FASTBUS master. It has been designed for crate-level readout and processing of data from TDC and FADC modules which instrument a new 6000-wire central drift chamber for the upgraded Mark II detector. The SSP, however, provides a general and powerful means of moving and processing data in a FASTBUS system. Therefore, it has also been adopted by the Mark II for use at the system-level as a cable-segment master and buffer module
Additional details
Publishing Information
- Journal Title
- IEEE Trans. Nucl. Sci.
- Journal Volume
- NS-32
- Journal Issue
- 1
- Series
- IEEE Trans. Nucl. Sci.
- Journal Page Range
- 336-340
- ISSN
- 0018-9499
- CODEN
- IETNA
Conference
- Title
- Nuclear science symposium.
- Dates
- 31 Oct - 2 Nov 1984.
- Place
- Orlando, FL (USA).
INIS
- Country of Publication
- United States
- Country of Input or Organization
- United States
- INIS RN
- 17068994
- Subject category
- S43: PARTICLE ACCELERATORS;
- Resource subtype / Literary indicator
- Conference
- Descriptors DEI
- DATA ACQUISITION; DATA PROCESSING; DIGITAL COMPUTERS; DRIFT CHAMBERS; EQUIPMENT INTERFACES; FASTBUS SYSTEM; MULTIWIRE PROPORTIONAL CHAMBER; STANFORD LINEAR ACCELERATOR CE
- Descriptors DEC
- COMPUTERS; MEASURING INSTRUMENTS; NATIONAL ORGANIZATIONS; PROPORTIONAL COUNTERS; RADIATION DETECTORS; US DOE; US ERDA; US ORGANIZATIONS
Optional Information
- Secondary number(s)
- CONF-841007--.