Evaluation of a (Bi,La)4Ti3O12 thin film capacitor fabricated on a sub-micron bottom electrode in a FeRAM device

A ferroelectric random access memory device was integrated with stacked (Bi,La)4Ti3O12 capacitors of 0.68 μm2 in area. The ferroelectric layer was coated on a patterned Pt/IrOx/Ir bottom electrode stack by using the spin-on method. The switchable polarization obtained in the 32k-array capacitors, which was equivalent to a large single capacitor of 22,300 μm2, was 16 μC/cm2 at 3 V operation, and the uniformity was excellent at 2.8%. However, failed cells were randomly detected when measuring the bit-line signal of each cell. Both the grain size and the crystallographic orientation in the BLT layer showed poor uniformity between cells. The microstructure was optimized by varying the temperature in the nucleation step. The optimization removed the bit failure in the fabricated BLT capacitors. Therefore, we successfully integrated a FeRAM device with sub-micron BLT capacitors. The cell signal margin of the device was 340 mV.