Impact of material properties and device architecture on the device performance for a gate all around nanowire tunneling FET

This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium–arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simulations were performed to investigate the underlying physics. Device on-off (I _on/I _off) ratio was considered as key figure-of-merit (FOM) to improve. It is observed that the off current (I _off) is a weak function of dielectric constant, however, the on current (I _on) increases from 1.51  ×  10⁻⁷ A µm⁻¹ to 1.79  ×  10⁻⁶ A µm⁻¹ as the dielectric constant increases from SiO₂ to La₂O₃. It was also observed that as the diameter increases, both I _on and I _off increases. I _on/I _off ratio is independent for higher channel lengths but as the channel length is reduced below 30 nm, I _off increases causing degradation in I _on/I _off ratio. Finally, the effect of interface traps was realised on the I _on/I _off ratio. Interface traps impact the flat-band voltage causing a shift in the device performance. It is observed that as the trap density increases, I _off degrades rapidly by ∼3 orders in magnitude. (paper)