Prototype of simultaneous bidirectional data-transmitter in 65 nm CMOS

This article presents a design and implementation of an I/O circuit block capable of simultaneous bidirectional data-transmission in CMOS integrated circuits. Merging data-transmitter and receiver into common bonding pad is feasible not only to reduce the number of transmission lines from a considerable number of chips, but also to realize more area-efficient data handling in consequence of flexible inter-chip communication. This feature is attractive from the viewpoint of detector systems in high energy experiments, in which reducing materials such as cables from silicon trackers in inner vertex layers is of major importance to suppress multiple-scattering and to achieve good overall detector performances. The circuit block presented here is designed on the basis of a current subtraction circuit and two distinct current-mode logic drivers. Its principle is also applicable to widely-used low-voltage differential signal drivers and easy for process migration. The prototype chip was fabricated in a 65 nm CMOS technology. Working principle has been demonstrated in preliminary laboratory testing. (technical report)