A CMOS matrix for extracting MOSFET parameters before and after irradiation

An addressable matrix of 16 n- and 16 p-MOSFETs has been designed to extract the DC MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs each with four different geometries that can be biased independently before and after irradiation. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Cobalt 60 irradiation results for the n-MOSFETs showed a very low threshold voltage shift of -3mV/krad(Si); whereas, the p-MOSFETs showed 21 mV/krad(Si). The worst-case threshold voltage shift occurred for the n-MOSFET with a gate bias of 5V during anneal, but for the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5V on the gate during irradiation