Published September 2011 | Version v1
Journal article

Numerical dc self-heating in planar double-gate MOSFETs

  • 1. IUMA, Institute for Applied Microelectronics, Universidad de Las Palmas de Gran Canaria, Edificio de Electrónica y Telecomunicación, Campus Universitario de Tafira, 35017, Las Palmas (Spain)
  • 2. Departament d'Enginyeria Electrònica, Elèctrica i Automàtica, Universitat Rovira i Virgili, Escola Tècnica Superior d'Enginyeria, Av. Dels Països Catalans, 26, 43007, Tarragona (Spain)
  • 3. Solid-State Electronics Section, CINVESTAV, Av. IPN 2508, 07360, Mexico D.F. (Mexico)

Description

Self-heating in planar double-gate (DG) MOSFETs is numerically studied under static operating conditions. In order to correctly predict the lattice temperature inside the device and, consequently, the drain current, factors such as the reduction in thermal conductivity of thin films (temperature dependent), the influence of the buried oxide layer, the necessity of a hydrodynamic model and quantization are analysed to evidence their impact on a proper simulation of the dc transistor performance. This paper also shows that DG MOSFETs can be thermally optimized using flare extensions in all terminals and mid-gap gate metals with high thermal conductivity. Moreover, the influence of gate length and channel thickness on the peak temperature rise is studied. Other major technological changes, such as eliminating thin oxide films from channel extensions and using AlN instead of SiO2, are also discussed

Availability note (English)

Available from http://dx.doi.org/10.1088/0268-1242/26/9/095014

Additional details

Identifiers

DOI
10.1088/0268-1242/26/9/095014;
PII
S0268-1242(11)95016-0;

Publishing Information

Journal Title
Semiconductor Science and Technology
Journal Volume
26
Journal Issue
9
Journal Page Range
[9 p.]
ISSN
0268-1242
CODEN
SSTEET