Published August 2013 | Version v1
Journal article

A replacement of high-k process for CMOS transistor by atomic layer deposition

  • 1. Center for Nanotechnology, NASA Ames Research Center, Moffett Field, CA 94035 (United States)
  • 2. Hewlett-Packard Co, 1501 Page Mill Rd., Palo Alto, CA 94304 (United States)
  • 3. Department of Electrical Engineering, KAIST, 291 Daehak-ro, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)

Description

A replacement of high-k process was implemented on an independent double gate FinFET, following the ordinary gate-first process with minor modifications. The present scheme involves neither exotic materials nor unprecedented processing. After the source/drain process, the sacrificial gate oxide was selectively substituted with amorphous Ta2O5 via conformal plasma enhanced atomic layer deposition. The present gate-first gate-dielectric-last scheme combines the advantages of the process and design simplicity of the gate-first approach and the control of the effective gate workfunction and the interfacial oxide of the gate-dielectric-last approach. Electrical characterization data and cross-sectional images are provided as evidence of the concept. (fast track communication)

Availability note (English)

Available from http://dx.doi.org/10.1088/0268-1242/28/8/082003

Additional details

Publishing Information

Journal Title
Semiconductor Science and Technology
Journal Volume
28
Journal Issue
8
Journal Page Range
[4 p.]
ISSN
0268-1242
CODEN
SSTEET

INIS

Country of Publication
United Kingdom
Country of Input or Organization
International Atomic Energy Agency (IAEA)
INIS RN
45013920
Subject category
S75: CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY;
Descriptors DEI
AMORPHOUS STATE; CONTROL; DEPOSITION; LAYERS; TANTALUM OXIDES; TRANSISTORS
Descriptors DEC
CHALCOGENIDES; OXIDES; OXYGEN COMPOUNDS; REFRACTORY METAL COMPOUNDS; SEMICONDUCTOR DEVICES; TANTALUM COMPOUNDS; TRANSITION ELEMENT COMPOUNDS