Published September 2014 | Version v1
Journal article

Analysis of interface trap states in InAlN/AlN/GaN heterostructures

  • 1. School of Physics, Shandong University, Jinan, 250100, People's Republic of China (China)
  • 2. National Key Laboratory of Application Specific Integrated Circuit (ASIC), Hebei Semiconductor Research Institute, Shijiazhuang, 050051, People's Republic of China (China)

Description

Gate-source frequency-dependent capacitance and conductance measurements were performed on the In0.17Al0.83N/AlN/GaN heterostructure field-effect transistor with side-Ohmic contacts to study the characteristics of trap states at the interface between InAlN and GaN. The values of interface trap state density and time constant were determined to be (0.96–3.36) × 1013 cm−2 eV−1 and (0.29–1.61) μs, respectively. We calculated the strain in the InAlN barrier layer under the gate and found that the InAlN barrier layer was compressively strained with the in-plane strain of 1.31%. This is a possible reason for such a high interface trap state density which is not as low as supposed in the lattice-matched heterostructures. (paper)

Availability note (English)

Available from http://dx.doi.org/10.1088/0268-1242/29/9/095011

Additional details

Publishing Information

Journal Title
Semiconductor Science and Technology
Journal Volume
29
Journal Issue
9
Journal Page Range
[5 p.]
ISSN
0268-1242
CODEN
SSTEET