System-level electrostatic discharge simulation based on transmission line pulse modeling

Effective protection can be conducted before an electronic system is measured through system-level ESD simulation. In this paper, the spice behavioral modeling for the transient voltage suppressor and IC pins are presented using the measured transmission line pulse (TLP) data. A system-level ESD simulation methodology is proposed, including the equivalent circuit model of ESD pulse source, S-parameter model of PCB board, TLP model of TVS protection diode, IC pins and co-simulation technology. A switch chip protect circuit is simulated and measured under IEC 61000-4-2 ESD stress. The good agreement between simulated and measured voltage waveforms demonstrates the effectiveness of the proposed simulation method. (authors)