Published September 21, 2014 | Version v1
Journal article

Valence and conduction band offsets at low-k a-SiOxCy:H/a-SiCxNy:H interfaces

  • 1. Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124 (United States)
  • 2. Ocotillo Materials Laboratory, Intel Corporation, Chandler, Arizona 85248 (United States)

Description

In order to understand the fundamental electrical leakage and reliability failure mechanisms in nano-electronic low-k dielectric/metal interconnect structures, we have utilized x-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy to determine the valence and conduction band offsets present at interfaces between non-porous and porous low-k a-SiOxCy:H interlayer dielectrics and a-SiCxNy:H metal capping layers. The valence band offset for such interfaces was determined to be 2.7 ± 0.2 eV and weakly dependent on the a-SiOC:H porosity. The corresponding conduction band offset was determined to be 2.1 ± 0.2 eV. The large band offsets indicate that intra metal layer leakage is likely dominated by defects and trap states in the a-SiOC:H and a-SiCN:H dielectrics.

Additional details

Identifiers

Publishing Information

Journal Title
Journal of Applied Physics
Journal Volume
116
Journal Issue
11
Journal Page Range
p. 113703-113703.6
ISSN
0021-8979
CODEN
JAPIAU

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