Design considerations for a radiation hardened nonvolatile memory

Sub-optimal design practices can reduce the radiation hardness of a circuit even though it is fabricated in a radiation hardened process. This is especially true for a nonvolatile memory, as compared to a standard digital circuit, where high voltages and unusual bias conditions are required. This paper will discuss the design technique's used in the development of a 64K EEPROM (Electrically Erasable Programmable Read Only Memory) to maximize radiation hardness. The circuit radiation test results will be reviewed in order to provide validation of the techniques