Gate stack engineering for GaN lateral power transistors

Developing optimal gate-stack technology is a key to enhancing the reliability and performance of GaN insulated-gate devices for high-voltage power switching applications. In this paper, we discuss current challenges and review our recent progresses in gate-stack technology development toward high-performance and high-reliability GaN power devices, including (1) interface engineering that creates a high-quality dielectric/III-nitride interface with low trap density; (2) barrier-layer engineering that enables optimal trade-off between performance and stability; (3) bulk quality and reliability enhancement of the gate dielectric. These gate-stack techniques in terms of new process development and device structure design are valuable to realize highly reliable and competitive GaN power devices. (paper)