Unified model of damage annealing in CMOS, from freeze-in to transient annealing

Irradiation studies at 760K are described which demonstrate that radiation-produced holes in SiO2 are immobile at this temperature. If an electric field of either polarity is present in the SiO2 during 760K irradiation, to sweep out the mobile electrons, the holes will virtually all be trapped where created and produce a uniform positive charge density in the oxide. This predicts ΔV/sub T/ varies as d/sub ox/2, which is observed. The magnitude of the observed shift is consistent with 18 eV required per hole-electron pair generated. All CMOS transistors of the same oxide thickness exhibit the same initial ΔV/sub T/, for a given exposure level, regardless of oxide type or process. The rate of annealing differs, both as a function of oxidation process and oxide thickness. Thin oxides have two advantages: a smaller ΔV/sub T/ (stable shift) and faster annealing. If a CMOS device is irradiated for sufficient time at 760K to build in an appreciable field, further irradiation with zero gate-substrate bias will produce little additional change in V/sub T/, since the field in the oxide tends to keep all generated electrons in the oxide, where they recombine with trapped holes. Room temperature annealing following a pulsed gamma exposure occurs in two regimes. The first regime can be quite fast, and occurs prior to 10-4 seconds. The magnitude of this early-time recovery is both process dependent and thickness dependent. In a hardened device most of the damage anneals during this early-time stage, whereas in a typical non-hardened unit the early-time stage (recovery) can be quite small