The design of high speed link board in BELLEⅡ

With the improved performance of accelerators and detectors in the high energy physics experiments, data acquisition (DAQ) system is facing more and more challenges of real time and reliable data transmission. BelleII, as a new type detector running on the high luminosity accelerator SuperKEKB, its DAQ system is facing the same pressure. The high speed link board (HSLB) has achieved a serial line rate up to 3.125 Gbps with the RocketIO technology based on Xilinx FPGA. The control chip CPLD connects to local interface, provides the function such as fast online FPGA configuration, high speed link data transmission and slow control. The HSLB hardware design and FPGA online configuration are introduced in the paper. The test results show that the HSLB can fulfill the critical requirements and small scale mass production is in schedule. (authors)