Published February 2016 | Version v1
Journal article

Transient performance estimation of charge plasma based negative capacitance junctionless tunnel FET

  • 1. Department of Electronics and Communication Engineering, PDPM-Indian Institute of Information Technology, Design and Manufacturing (IIITDM) Jabalpur Jabalpur, MP (India)

Description

We investigate the transient behavior of an n-type double gate negative capacitance junctionless tunnel field effect transistor (NC-JLTFET). The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n+ silicon channel and a ferroelectric gate stack to get negative capacitance behavior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well. (paper)

Availability note (English)

Available from http://dx.doi.org/10.1088/1674-4926/37/2/024003

Additional details

Publishing Information

Journal Title
Journal of Semiconductors
Journal Volume
37
Journal Issue
2
Journal Page Range
[5 p.]
ISSN
1674-4926