Design of an area and energy-efficient last-level cache memory using STT-MRAM

This paper presents an area and energy-efficient non-volatile Last-level Cache (LLC) using a STT-MRAM based on a state-of-art perpendicular magnetic tunnel junction (pMTJ) and an Vertical Gate-All-Around Field-Effect Transistor (GAA-FET). This work presented, in this article is carried out from device to circuit, architecture and up to the system level. A detailed analysis of STT-MRAM has been presented by comparing an Vertical GAA-FET (GA) with a bulk-FET (B) at cell level. It is observed that GA-STT-MRAM is advantageous and offers 93.10% and 60% reduction in leakage-power dissipation and area, respectively over B-STT-MRAM. Furthermore, at architecture level, 20% to 80% reduction in sizes of LLCs (ranging from 512 KB to 64 MB) is observed by using GA-STT-MRAM and around 80.78% leakage power reduction is achieved in comparison to SRAM based LLCs. In addition to the architecture level, GA-STT-MRAM is found to have 83.26% and 39.40% energy reduction compared to a B-STT-MRAM and a conventional SRAM, respectively at system level. The GA-STT-MRAM proves to be a more promising candidate to replace conventional semiconductor based LLC for next-generation energy-efficient microprocessors having on-chip non-volatility.