Electrical characterization of in-place bonded interfaces

Wafer bonding using an intermediate layer such as SiO₂ is now a standard method for the fabrication of engineered substrates in the semiconductor industry, the prime example being silicon-on-insulator (SOI) substrates. However, direct semiconductor-to-semiconductor bonding by this method has been less successful, since the surfaces to be bonded are typically exposed to air. With the in-place bonding method, semiconductor-to-semiconductor bonding occurs during removal of a sacrificial layer in an HF solution, in principle allowing for a bonded interface that is free of oxygen and other airborn contaminants. We have investigated the interface properties of in-place bonded GaAs/GaAs structures with both transmission electron microscopy and current–voltage measurements. The interface was found to be free of an oxide interlayer and microstructure imperfections. The specific electrical resistance is (2.2 ± 0.5) × 10⁻⁴ Ω cm², an order of magnitude lower than values reported for wafer bonded interfaces. (papers)