A high voltage SOI pLDMOS with a partial interface equipotential floating buried layer

A novel silicon-on-insulator (SOI) high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer (FBL) and its analytical model is analyzed in this paper. The surface heavily doped p-top layers, interface floating buried N+/P+ layers, and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance. On the condition of ESIMOX (epoxy separated by implanted oxygen), it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from −232 V of the conventional SOI to −425 V and the specific resistance Ron,sp is reduced from 0.88 to 0.2424 Ω·cm2. (semiconductor devices)