A 4 × 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications

In ultra-low-power applications, the design of power-efficient static random access memory (SRAM) is a major concern as it plays a significant part in leakage due to its higher density. In this paper, we have designed a power-efficient SRAM array that efficiently utilizes our SRAM cell for low-power and reliable memory applications. The proposed SRAM array is designed with an optimized 8T SRAM cell with minimum leakage and improved stability. The cell designed with 22 nm CMOS technology uses a stacking effect to further enhance leakage reduction and transmission gate as an access transistor to obtain better stability. Peripheral circuitry like address decoder, write driver, pre-charge, and sense amplifier are designed with optimum transistor sizing to get superior results in terms of area occupied and power consumption. The read and write access time for the cell is found to be 12 ps and 10 ps respectively. In line with the 22 nm technology node, the power is calculated for the array as 0.42 µW. (paper)