Shielding design for a chip irradiation test facility at SNS - Paper 119

As digital and analog circuits are more and more sophisticatedly integrated, they become increasingly susceptible to single event upsets (SEU), a cause of electronic equipment malfunction induced by cosmic rays with particular hazard potential for aviation equipment. Electronic chips sensitive to SEU have to be tested in a simulated comic ray environment to ensure their reliability. It is found that the spallation induced fast neutron spectrum is very close to the neutron spectrum of the cosmic ray. Hence, a conceptual design study of a chip irradiation test facility is funded by FAA to be carried out at SNS, the world's most powerful accelerator driven facility for neutron scattering studies on materials. Compared to existing/being construct chip irradiation test facilities at LANL and ISIS, SNS can provide wider neutron energy range and much higher fluxes. This study focuses on the aspect of shielding design for such a chip irradiation facility. A number of medium-weighted and heavy materials were examined for efficiency in reducing radiation dose rate. In general, the smaller the target monolith is while satisfying the personnel-protection-driven radiation dose rate limit at its outside, the closer to the target chips could be placed and thus less beam power it demands to satisfy a given irradiation flux requirement. Before proceed to the shielding design, the neutron source coming off the target has to be determined for selecting a best spot for chip irradiation test, in which the incoming fast neutron spectrum approximate most to the atmospheric radiation condition. It also provides a source term for the following shielding design of the irradiation enclosure. (authors)