Simulation study of scaled In_0.53Ga_0.47As and Si FinFETs for sub-16 nm technology nodes

We investigate the performance and scalability of III-V-OI In_0.53Ga_0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths ( L _G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I _ON/ I _OFF ratio (5.9 × 10⁴ when L _G = 12.8 nm and 5.7 × 10⁴ when L _G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts. (paper)