A fast programmable trigger for pattern recognition

We have built a fast programmable trigger processor based on a state-of-the-art field programmable gate array (FPGA) IC for the Palo Verde Neutrino Oscillation Experiment. The trigger processor can accommodate 160 ECL input signals, 8 NIM input signals, 16 ECL output signals and 8 NIM output signals. Our two-level trigger logic is designed asynchronously to maximize speed. We have attained trigger times of 40 ns for level 1 and 100 ns for level 2 with 132 asynchronous inputs. The trigger processor can be upgraded by replacing the FPGA with more advanced versions of the chip as they appear. (orig.)