Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack

Highlights: •The device with HfO₂/TiO₂/SiO₂ gate stack shows good electrical performance. •The interface at the front-channel can be improved by a thin SiO₂ interfacial layer. •With Ga₂O₃ interfacial layer, a positive shift of threshold voltage can be achieved. •The physical analysis and energy band model of device are well discussed in detail. -- Abstract: The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO₂/TiO₂/HfO₂) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO₂ or Ga₂O₃) are also discussed in this report. The devices with SiO₂ interfacial layer show a high on/off current ratio of ~7 × 10⁷ for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm²/Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication.