EFTEM and EELS SI: tools for investigating the effects of etching processes for III-V MOSFET devices

High quality oxides layers are now available for MOSFETs on GaAs. For successful devices, suitable process schemes are required. In this paper we show an investigation of an etching process on a GaAs/Ga2O3/GGO dielectric gate stack. This investigation has been carried out using EFTEM and EELS SI. EFTEM provides a quick analysis on the structure while EELS SI offers much better resolution and the possibility to quantitatively characterize the material.