Published December 1990
| Version v1
Journal article
Latch-up CMOS/EPI devices
Creators
- 1. Centre National d'Etudes Spatiales, 18 Av. Edouard Belin, 31055 Toulouse Cedex (France)
- 2. Z.I. Flourens, 31130 Balma (France)
- 3. Inst. de Physique Nucleaire, BP 1-91406, Orsay Cedex (France)
Description
New space projects tend to use more and more VLSI circuits manufactured in CMOS technology. Assessment of latch-up sensitivity is mandatory in the evaluation plan of a component, and in some cases the result could be considered as a GO/NOGO parameter. The authors present data on several CMOS/EPI devices demonstrating the non-efficiency of an epitaxial layer to achieve latch-up immunity for some latest technologies
Additional details
Publishing Information
- Journal Title
- IEEE Transactions on Nuclear Science
- Journal Volume
- 37
- Journal Issue
- 6
- Series
- IEEE Trans. Nucl. Sci.
- Journal Page Range
- 1839-1842
- ISSN
- 0018-9499
- CODEN
- IETNA
Conference
- Title
- 27. IEEE annual conference on nuclear and space radiation effects.
- Dates
- 16-20 Jul 1990.
- Place
- Reno, NV (USA).
INIS
- Country of Publication
- United States
- Country of Input or Organization
- United States
- INIS RN
- 22056398
- Subject category
- S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY; S42: ENGINEERING;
- Resource subtype / Literary indicator
- Conference
- Descriptors DEI
- EPITAXY; INTEGRATED CIRCUITS; PHYSICAL RADIATION EFFECTS; SENSITIVITY; THIN FILMS
- Descriptors DEC
- ELECTRONIC CIRCUITS; FILMS; RADIATION EFFECTS
Optional Information
- Secondary number(s)
- CONF-900723--.