Towards new analog read-out electronics for the HADES drift chamber system

Track reconstruction in HADES is realized with 24 planar, low-mass drift chambers (MDC). About 27000 drift cells provide both, precise spatial information of track hit points and energy loss information. In order to handle high rates and track densities expected at the future SIS100 accelerator at FAIR, an upgrade of the MDC system is mandatory. Besides employing an advanced FPGA based TDC concept, this involves new analog front-end electronics, as the original analog read-out ASIC (ASD8) is no longer procurable. A promising replacement read-out chip candidate is the PASTTREC ASIC (developed at Jagiellonian University, Krakow), which is currently at the focus of our investigations. To assess its compatibility with MDC, PASTTREC was challenged in three different test environments (alongside with the ASD8 ASIC for reference): A cosmic muon tracking set-up at GSI detector lab, a 2.7 MeV/c proton beam test at COSY (FZ Juelich) and a UV LASER set-up at Helmholtz-Zentrum Dresden-Rossendorf. Emphasis is placed on assessing the timing precision of the joint system comprising detector and front-end electronics. The latter set-up, in addition, allows to study drift cell properties due to its unique ability to map the drift-time w.r.t. position over the entire cell. This contribution presents and compares the results of the abovementioned measurements.