A novel readout chip for silicon strip detectors with analog pipeline and digitally controlled analog signal processing

A readout chip for silicon strip detectors with analog event pipeline has been fabricated (SACMOS 2 μm technology) and tested. The chip has been designed to operate at the HERA ep collider at a bunch crossing rate of 10.4 MHz. Each channel has a layout width of 44 μm and consists of a fast, low noise, low power preamplifier followed by a switched capacitor analog event pipeline. The preamplifier consists of a single CMOS push-pull gain cell and offers minimal power consumption. A novel feature of our chip is a self-reading architecture that allows the preamplifier to re-read its own pipeline buffers and thus permits a extensive parallel analog signal processing that is digitally controlled. The results from radiation damage tests with 60Co are given for doses up to 240 krad. (orig.)