Published June 24, 2011
| Version v1
Journal article
A stacked memory device on logic 3D technology for ultra-high-density data storage
Creators
- 1. Device Research Laboratory, Department of Electrical Engineering, University of California, Los Angeles, CA 90095 (United States)
- 2. Advanced Technology Development Team and Process Development Team, Memory R and D Center, Samsung Electronics Co. Ltd (Korea, Republic of)
Description
We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.
Availability note (English)
Available from http://dx.doi.org/10.1088/0957-4484/22/25/254006Additional details
Identifiers
- DOI
- 10.1088/0957-4484/22/25/254006;
- PII
- S0957-4484(11)60829-5;
Publishing Information
- Journal Title
- Nanotechnology (Print)
- Journal Volume
- 22
- Journal Issue
- 25
- Journal Page Range
- [7 p.]
- ISSN
- 0957-4484
INIS
- Country of Publication
- United Kingdom
- Country of Input or Organization
- International Atomic Energy Agency (IAEA)
- INIS RN
- 43026827
- Subject category
- S77: NANOSCIENCE AND NANOTECHNOLOGY;
- Descriptors DEI
- ARCHITECTURE; DENSITY; EFFICIENCY; EQUIPMENT; MEMORY DEVICES; NANOSTRUCTURES; STORAGE; VERTICAL INTEGRATION
- Descriptors DEC
- PHYSICAL PROPERTIES