Soft-error on memory ICs induced by D-T neutrons

In order to examine the fusion neutron induced soft-error on memory ICs, several kinds of CMOS SRAM ICs were irradiated around room temperature with 14 MeV neutrons from OKTAVIAN. The pattern and rate of soft-error upsets on the ICs were measured in situ during neutron irradiation. It was found that neutron reactions caused not multiple but single type soft-errors and the number of the soft-errors increased proportionally with neutron fluence. There was also a large difference in the soft-error upset rate between set (from 0 to 1) and reset (from 1 to 0) soft-errors for some kinds of ICs. Considering the cell population in a chip, we obtained the neutron susceptibility constant, i.e. bit soft-error cross section of 2∼3 x 10-15 cm2 for 16K and 64K bit CMOS SRAM ICs, and 6∼9 x 10-14 cm2 for 256K and 1 Mbit ICs, respectively. Also, all memory cells were controllable after neutron irradiation and no permanent damage was caused by neutron fluence irradiation below about 1012n/cm2. (author)