A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

A new ultralow gate–drain charge (Q _GD) 4H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures (DS-MOS): one is the grounded split gate (SG), the other is the P⁺ shielding region (PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance (C _GD) into the gate–source capacitance (C _GS) and drain–source capacitance (C _DS) in series. Thus the C _GD is reduced and the proposed DS-MOS obtains ultralow Q _GD. Compared with the double-trench MOSFET (DT-MOS) and the conventional trench MOSFET (CT-MOS), the proposed DS-MOS decreases the Q _GD by 85% and 81%, respectively. Moreover, the figure of merit (FOM), defined as the product of specific on-resistance (R _{on, sp}) and Q _GD (R _{on, sp} Q _GD), is reduced by 84% and 81%, respectively. (paper)