Trend of tunnel magnetoresistance and variation in threshold voltage for keeping data load robustness of metal–oxide–semiconductor/magnetic tunnel junction hybrid latches

The robustness of data load of metal–oxide–semiconductor/magnetic tunnel junction (MOS/MTJ) hybrid latches at power-on is examined by using Monte Carlo simulation with the variations in magnetoresistances for MTJs and in threshold voltages for MOSFETs involved in 90 nm technology node. Three differential pair type spin-transfer-torque-magnetic random access memory cells (4T2MTJ, 6T2MTJ, and 8T2MTJ) are compared for their successful data load at power-on. It is found that the 4T2MTJ cell has the largest pass area in the shmoo plot in TMR ratio (tunnel magnetoresistance ratio) and Vdd in which a whole 256 kb cell array can be powered-on successfully. The minimum TMR ratio for the 4T2MTJ in 0.9 V < Vdd < 1.9 V is 140%, while the 6T2MTJ and the 8T2MTJ cells require TMR ratio larger than 170%