Online data reduction with FPGA-based track reconstruction for the Belle II DEPFET Pixel Detector [Session: T 18.9]

The innermost two layers of the Belle II vertex detector at the KEK facility in Tsukuba, Japan, will be covered by high-granularity DEPFET pixel sensors (PXD). The large number of pixels leads to a maximum data rate of 256 Gbps, which has to be significantly reduced by the Data Acquisition System. For the data reduction the hit information of the surrounding Silicon strip Vertex Detector (SVD) is utilized to define so-called Regions of Interest (ROI). Only hit information of the pixels located inside these ROIs are saved. The ROIs for the PXD are computed by reconstructing track segments from SVD data and extrapolating them to the PXD. The goal is to achieve a data reduction of up to a factor of 10 with this ROI selection. All the necessary processing stages, the receiving, decoding and multiplexing of SVD data on 48 optical fibers, the track reconstruction and the definition of the ROIs will be performed by the Data Acquisition Tracking and Concentrator Online Node (DATCON). The planned hardware design is based on a distributed set of Advanced Mezzanine Cards (AMC) each equipped with a Field Programmable Gate Array (FPGA). In this talk, the recent PHASE2 results as well as the plans for the upcoming PHASE3 are presented.