Improvement and evaluation of the high-frequency operation of superconductor frame compression circuits

We proposed previously a superconductor frame compression circuit utilized in superconductor high-speed routers, which were expected to be used in the next generation network. The maximum operating frequency of the circuit was 23 GHz in the simulation. It was limited by the arrival timing-error between clock and data signal in one of the shift register. In this paper we analyzed this timing-error. And we designed a modified clock supply circuit. The behavior of the whole frame compression circuit was simulated by computers, and it was confirmed that it operated properly up to 40 GHz